EE4743 Lab #3 - Dice Generator
In this lab we are going to build a dice generator. We will use this in a future lab in which we build a dice game.  The inputs/outputs of the dice generator are as follows:
Inputs:

	clk 		system clock
	reset		reset line 
	roll		when asserted, we will simulate rolling the dice

Outputs:

	dice_a[2:0]	the current value of dice_a
	dice_b[2:0]	the current value of dice_b
	sum		the bcd sum of dice_a and dice_b values
	valid		asserted when the dice_a, dice_b and sum outputs are stable
			after a roll request has been made.
Datapath
The datapath block diagram of the dice generator is shown in an attached figure.  The components of the datapath are as follows:
16-bit PRSG:  We will use a 16-bit Psuedo Random Sequence Generator (PSRG) to help simulate the dice roll.  This particular 16-bit PRSG is a shift register which shifts from LSB to MSB each clock cycle; the shift-in value is the exclusive-OR of bits 6, 8, 11, 15 (MSB) and the roll input.  When roll is a 1 the PSRG is guaranteed to generate the maximum sequence of 65536 different values before repeating. When roll is ’0’ a different sequence is generated which could have a much shorter period. 
dice_a, dice_b registers: These two registers will contain the current dice values; they should only be loaded if their three-bit input values are in the range from 1 to 6; all other values should be rejected.  You can connect the inputs of these registers to any groups of three bits from the PSRG - the 3 bit groups you use from the PRSG do not have to be contiguous or arranged in any particular order.  The only restraint is that the dice register inputs should use different bits of the PRSG. 
range check: This block  asserts  valid_a when the Dice Reg A inputs are in the range 1 to 6; valib_b is asserted when the Dice Reg B inputs are in the range 1 to 6.  The valid_a and valid_b signals are used by the control logic to ensure that the dice registers are not loaded with invalid dice values.
BCD adder: This block will generate a 5-bit BCD sum from its two 3-bit binary inputs. 
Control
The control state chart is shown in the attached figure.  The primary job of the control is to ensure that the A and B dice registers are loaded with values between 1 and 6 -- all other values are out of range.  The roll input should be asserted to begin the roll.  The valid output will be negated during rolling; once the A and B registers are loaded with new values the valid output will be asserted.  
VHDL Modeling
You are to implement this design using the Viewlogic VHDL synthesis tool.  You can write a VHDL model for each separate block or combine one or more functional blocks within one VHDL model (I wrote one VHDL model for the entire design but I strongly recommend that you write separate VHDL models for each of the functional blocks and use schematic capture to tie the functional blocks together).  
Normally you would not synthesize a datapath element like an adder with VHDL but since this adder is so small (only 3 bits) I will require you to synthesize the adder via VHDL.  The ’addum’ statement  should be used to synthesize the adder; note that the output of the adder must be in BCD.
You must use the ’itd2’ synthesis library for your design.
Report
For your report you must turn in a screen capture of your schematic, a printout of all VHDL models written, and a screen capture of a simulation of three successive rolls.   You must also prove that your simulation matches the expected results for your design - this means that you should figure out with pen and pencil what your dice generator should produce for the first three rolls - show all of this work in your report.
You should get started on this as soon as possible.  This lab will definitely take longer than the assigned lab period to get working - you should have all of your VHDL models written BEFORE you come to lab (you probably should already  have them typed in - there are plenty of terminals around the building for text-editing; you can also use a PC and call in via MODEM to enter your models.  The phone numbers for off-campus access are 325-2860 (2400 baud) and 325-2830 (1200 baud).  These are rotaries with several modems attached to each number.
The due date for this lab will be the beginning of your lab period during the week of Sept 21st; you will be given Lab #4 at this time.
Dice Generator Datapath

Dice Generator Control

Dice Generator Control (cont.)

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