Microsystems Prototyping Laboratory

invf104: 4X INVERTING BUFFER

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------
A	O
---------
0	1
1	0
---------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	15	34	70.7	34.8	22.7
O	76	34	-	-	-
--------------------------------------------

• Delay Information