Cell invf103: 3X INVERTING BUFFER

Microsystems Prototyping Laboratory

invf103: 3X INVERTING BUFFER

Gate Level Schematic
Transistor Level Schematic
Layout
Logic Equation
Inputs
Outputs
Truth Table
Terminal Location and Capacitance
Characterization Data

Gate Level Schematic of the standard cell "invf103".

Schematic of the standard cell "invf103" with device sizes in lambda.

Layout of the standard cell "invf103"

here.

Logic Equation: O = A1'

Input(s): A1

Output(s): O

Truth Table

---------
A	O
---------
0	1
1	0
---------

Terminal Location and Capacitance Table

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	12.5	28	71.0	35.0	22.8
O	49	28	-	-	-
--------------------------------------------

Characterization Data

Delay Information