Cell cgf104: TWO PHASE NON-OVERLAPPING CLOCK GENERATOR

Microsystems Prototyping Laboratory

cgf104: TWO PHASE NON-OVERLAPPING CLOCK GENERATOR

Gate Level Schematic
Transistor Level Schematic
Layout
Logic Equation
Inputs
Outputs
Truth Table
Terminal Location and Capacitance
Characterization Data

Gate Level Schematic of the standard cell "cgf104".

Schematic of the standard cell "cgf104" with device sizes in lambda.

Layout of the standard cell "cgf104"

here.

Logic Equation:

Input(s): CLK1

Output(s): PHI1, PHI2

Truth Table

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-----------------------

Terminal Location and Capacitance Table

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK1	6.5	34	137	67.4	43.7
PHI1	257	26	-	-	-
PHI2	188	26	-	-	-
--------------------------------------------

Characterization Data

Delay Information