Microsystems Prototyping Laboratory

buff101: NON-INVERTING BUFFER

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------
A	O
---------
0	0
1	1
---------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	14.5	20	49.6	23.3	14.7
O	28	18	-	-	-
--------------------------------------------

• Delay Information