std_ulogic type
This type is used to represent the value of a digital signal in a wire.
For general use, you probably want the std_logic instead.
A signal or variable of this type can take on the following values:
'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care.
The basic VHDL logic operations are defined on this type:
and,
nand,
or,
nor,
xor,
xnor,
not. They can be used like the built-in operations on the bits.