-- verify the setup time on W and R signals
-- we assume W and R are asserted alternatingly
timing_check: process
variable w_asserted: time;
variable r_asserted: time;
begin
-- wait for DUT to be reset
wait until RST = '1';
wait until RST = '0';
-- verify write access
wait until W = '0';
w_asserted := now;
wait until W = '1';
print("I@TB: detected W access");
assert (now - w_asserted) >= tSU_W
report "E@TB: W setup time too short"
severity Error;
-- verify read access
wait until R = '0';
r_asserted := now;
wait until R = '1';
print("I@TB: detected R access");
assert (now - r_asserted) >= tSU_R
report "E@TB: R setup time too short"
severity Error;
end process timing_check;
Rerunning the simulation, the problem becomes immediately apparent:
VSIM 31> run -all
# I@TB: detected W access
# I@TB: detected R access
VSIM 32>
The transaction log contains an insufficient number of write and read cycles. The problem can be fixed in the timing checker as shown:
-- wait for DUT to be reset
wait until RST = '1';
wait until RST = '0';
loop
-- verify write access
wait until W = '0';
...
end loop;
end process timing_check;
And now the problem in the circuit is detected:
VSIM 8> run -all
# I@TB: detected W access
# I@TB: detected R access
# I@TB: detected W access
# I@TB: detected R access
# ** Error: E@TB: R setup time too short
# Time: 64 ns Iteration: 0
# I@TB: detected W access
VSIM 9>
In order to effectively work with transaction logs it's helpful to write them to files. Here is a way to do this with the MTI simulator:
vsim tb1 -c -do "run 400 ns ; exit -f" > sim.log
These logs should be kept for each test, so that in a later simulation run the current log can be automatically compared with the golden log.
Below are the files which have been simulated in this section:
 |
|
|
| txt_util.vhd | hang2.vhd | tloop.vhd |
